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feds5424331-01 1 semiconductor this version: sep. 2000 msm5424331 222,720-word 24-bit field memory 1/34 general description the msm5424331 is an image data processing field memory organized as 222,720 (768 pixels by 290 lines) by 24 bits that can switch between the fifo mode where the msm5424331 is used as an ordinary field memory and a block access mode where the msm5424331 can easily exchange data with personal computer and the like. serial writing in and serial reading from the msm5424331 are performed line by line. in the fifo mode, any line can be selected by specifying their addresses by the serial address input. in the block access mode, any line or word address (10 bits) can be set by entering the address through the address multiplexer. as the msm5424331 in the block access mode can be controlled by ras and cas signals, it can easily interface to the mpu. the msm5424331 contains dynamic memory cells. in the fifo mode, the memory cells are automatically refreshed by the self refresh control circuit, but in the block access mode, the memory cells must be refreshed by the cas before ras refresh function. the msm5424331 is not designed for high end use in such applications as medical systems, professional graphics systems which require long term picture storage, data storage systems and others.
feds5424331-01 1 semiconductor msm5424331 2/34 features ? switching between fifo and block access modes by the d/f pin fifo mode: serial write/read operation by line-by-line accessing block access mode: fast write/read operation on an 8-word basis by the ras and cas control ? organization of 768 290 24 bits fifo mode: input 12 or 24 controlled by l/uwe output 24 block access mode: input 12 (two 768 290 12-bit banks are controlled by l/uwe .) output 12 (two 768 290 12-bit banks are controlled by a9.) ? asynchronous operation input and output asynchronous operation enabled only in the fifo mode single write or read operation in the block access mode ? serial read and write cycle times (in both the fifo mode and the block access mode) cycle time: 60 ns access time: 50 ns ? operating supply voltage: 2.8 to 3.3 v ? refresh fifo mode: self refresh block access mode: by the cas before ras refresh function (290 cycles/8 ms) ? address input fifo mode: setting random line address by the serial address input block access mode: setting random address in the address multiplexer by the ras and cas control ? selectable serial address input setting or various address resetting in the fifo mode ? package: 70-pin 400 mil plastic tsop (type 2) (tsop(2)70-p-400-0.50-k) (product: MSM5424331TS-AK)
feds5424331-01 1 semiconductor msm5424331 3/34 pin configuration (top view) rade/rx rclk r e do0[dq0] do1[dq1] do2[dq2] do3[dq3] do4[dq4] do5[dq5] v ss do8[dq8] do9[dq9] do10[dq10] do11[dq11] v cc v cc do12 do14 do15 do13 do6[dq6] do7[dq7] do16 do17 do19 do20 do21 do22 do23 wxinc wr/tr wxad wade/rx v cc do18 rxad rr rxinc v ss d/f din0[ ras ] din1[ cas ] din2[a0] din3[a1] din4[a2] din7[a5] din8[a6] din9[a7] din10[a8] din11[a9] wait v ss din13 din14 din12 din5[a3] din6[a4] din15 din16 din19 din20 din21 din22 din23 wclk l we ie u we din17 din18 70-pin plastic tsop ( 2 ) (k type) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36
feds5424331-01 1 semiconductor msm5424331 4/34 pin name fifo mode fifo mode block mode address setting cycle serial read/write cycle block mode rclk read x serial address strobe serial read clock ? re re ? read enable read enable do0 - 11 dq0 - 11 ? data output data input/output do12 - 23 ? data output ? rr read address reset mode enable ? ? rxinc read x address increment ? ? rade/rx read x address input enable read x address reset ?? rxad read x serial address data ? ? wclk write x serial address strobe serial write clock ? lwe lwe ? write enable write enable uwe uwe ? write enable write enable ie ? input enable ? din0 ras ? data input x address strobe din1 cas ? data input y address strobe din2 - 11 a0 - a9 ? data input address input din12 - 23 ? data input ? wr/tr write address reset mode enable write data transfer ? wxinc write x address increment ? ? wade/rx write x address input enable write x address reset ?? wxad write x serial address data ? ? wait ? ? external synchronous signal d/f d/f mode change (d/f = l) mode change (d/f = h) v cc power supply voltage (3.0 v) v ss ground (0 v) note: same power supply voltage level must be provided to every v cc pin. same ground voltage level must be provided to every v ss pin.
feds5424331-01 1 semiconductor msm5424331 5/34 block diagram block mode control fifo mode control ra s wcl k wr/t r wade/r x wxad wxinc rcl k r r rade/r x rxad rxinc ca s lw e uw e a0-a9 v bb generator refresh control ra s ca s mode control d/f memory controller wait x-decoder read register write register write register l-bank memory cell array (760 290 12) x-decoder read register u-bank memory cell array (760 290 12) dout buffer re 12 dout buffer re 12 write buffer write buffer u we ie 12 dout12-23 din12-23 12 din0-11 ie l we dq0-11 12 dq0-11 dout0-11 12
feds5424331-01 1 semiconductor msm5424331 6/34 pin function read related d/f this signal switches between the fifo mode and the block access mode. the fifo mode is selected when this signal is low ?l? and the block access mode is selected when this signal is high ?h?. rclk: read clock rclk is the read control clock input in the fifo mode. synchronized with rclk?s rising edge, serial read access from read ports is executed when re is low. the internal counter for the serial read address is incremented automatically on the rising edge of rclk. in a read address set cycle, all the read address bits which were input from rxad pin are stored into internal address registers synchronized with rclk. in this address set cycle, rade/rx must be held high and rr must be held low. in the read address reset cycle, various read address reset modes can be set synchronously with rclk. these reset cycles work to replace complicated serial address control which requires many rclk clocks with a simple reset cycle control requiring only a single rclk cycle. it greatly facilitates memory access. in the block access mode, the rclk signal is ignored. re : read enable re is a read enable clock input in the fifo mode. re enables or disables both internal read address pointers and data-out buffers. when re is low, the internal read address pointer is incremented synchronously with rclk. when re is high, even if the rclk is input, the internal read address pointer is not incremented. the output pins are enabled in the read cycle of the block access mode when this pin ( re ) is low ?l?. rr: read reset rr is a read reset control input in the fifo mode. read address reset modes are defined when rr level is high according to the ?function table for read?. in the block access mode, the rr signal is ignored. rxinc: read x address increment rxinc is a read x address (or line address) increment control input in the fifo mode. in the read address reset cycle, defined by rr high, the x address (or line address) is incremented by 1 when rxinc is pulled high with rade/rx low. in the block access mode, the rxinc signal is ignored. rade/rx: read address enable/read x address reset logic function rade/rx is a dual function control input in the fifo mode. rade, one of the two functions of rade/rx, is a read address enable input. in the read address set cycle, x address (or line address) input from the rxad pin is latched into internal read x address register synchronously with rclk. rx, the second function of rade/rx, works as an element to set read x address (or line address) reset mode. in an address reset mode cycle, defined by rr high, read x address is set to 0 when rade/rx is pulled high with rxinc low. in the block access mode, the rade/rx signal is ignored.
feds5424331-01 1 semiconductor msm5424331 7/34 rxad: read x address rxad is a read x address (or line address) input in the fifo mode. rxad specifies the line address. 10 bits of read x address data are input serially from rxad. the bits of an address are fetched starting from the higher order bits. the most significant bit (a9) is ignored. in the block access mode, the rxad signal is ignored. do0-11 (dq0-11), do12-23: data-outs in the fifo mode, these pins are used as serial outputs. in the block access mode, pins do0 to do11 (dq0 to dq11) are used as input and output pins.
feds5424331-01 1 semiconductor msm5424331 8/34 write related wclk: write clock wclk is a write control clock input in the fifo mode. synchronized with wclk?s rising edge, serial write access into write ports is executed when lwe or uwe is low. according to wclk clocks, the internal counter for the serial address is incremented automatically. in a write address set cycle, all the write addresses which were input from wxad are stored into internal address registers synchronously with wclk. in this address set cycle, wade/rx must be held high and wr/tr must be held low. in the write address reset cycle, various write address reset modes can be set synchronously with wclk. these reset cycles replace complicated serial address control with simple reset cycle control which requires only one wclk cycle. it greatly facilitates memory access. in the block access mode, the wclk signal is ignored. lwe : write enable lwe is a write enable clock input in the fifo mode. lwe enables or disables both internal write address pointers and data-in buffers. when lwe is low, the internal write address pointer is incremented synchronously with wclk. when lwe is high, even if wclk is input, the internal write address pointer is not incremented. in the block access mode, writing in the l-bank is performed when lwe goes low at the falling edge of din0 (ras ). uwe : write enable uwe is a write enable clock input in the fifo mode. uwe enables or disables both internal write address pointers and data-in buffers. when uwe is low, the internal write address pointer is incremented synchronously with wclk. when uwe is high, even if wclk is input, the internal write address pointer is not incremented. in the block access mode, writing in the u-bank is performed when uwe goes low at the falling edge of din0 ( ras ). din0 ( ras ): data-in din0 is serial data-in in the fifo mode. in the block access mode, this pin serves as ras . on the falling edge of this signal, the 10-bit row address (a0 to a9) is fetched. din1 ( cas ): data-in din1 is serial data-in in the fifo mode. in the block access mode, this pin serves as cas . on the falling edge of this signal, the 10-bit column address (a0 to a9) is fetched. this column address becomes a start address in the block access mode. when din1 ( cas ) is toggled while din0 ( ras ) remains low, the read/write operation in the block access mode is enabled. din2-11 (a0-a9): data-ins din2-11 are serial data-ins in the fifo mode. in the block access mode, these pins serve as a row or column address input (a0 to a9). these pins fetch a row address when din0 ( ras ) is active or a column address when din1 ( cas) is active. din12-23: data-ins din12-23 are serial data-ins in the fifo mode.
feds5424331-01 1 semiconductor msm5424331 9/34 wr/tr: write reset/write transfer wr/tr is a write reset control input in the fifo mode. write address reset modes are defined when wr/tr level is high according to the ?function table for write?. when the write operation on a line is terminated, be sure to perform a write transfer operation by wr/tr in order to store the written data in the write register to corresponding memory cells. in the block access mode, the wr/tr signal is ignored. wxinc: write x address increment wxinc is a write x address (or line address) increment control input in the fifo mode. in the write address reset cycle, defined by wr/tr high, the write x address (or line address) is incremented by 1 when wxinc is pulled high with wade/rx low. in the block access mode, the wxinc signal is ignored. wade/rx: write address enable/write x address reset logic function wade/rx is a dual functional control input in the fifo mode. wade, one of the two functions of wade/rx, is a write address enable input. in the write address set cycle, x address (or line address) input from the wxad pin is latched into internal write x address register synchronously with wclk. rx, the second function of wade/rx, works as an element to set write x address (or line address) reset mode. in the write address reset cycle, defined by wr/tr high, the write x address is set to 0 when wade/rx is pulled high with wxinc low. in the block access mode, the wade/rx signal is ignored. wxad: write x address wxad is a write x address (or line address) input in the fifo mode. wxad specifies line address. 10 bits (0 to 9) of write x address data are input serially from wxad. the bits of an address is fetched starting from the higher order bits. the most significant bit (a9) is ignored. in the block access mode, the wxad signal is ignored. ie: input enable ie is an input enable in the fifo mode which controls the write operation. when ie is high, the input operation is enabled. when ie is low, the write operation is masked. when lwe and uwe signals are low, and ie low, the internal serial write address pointer is incremented on the rising edge of wclk without actual write operations. this function facilitates picture in picture function in a tv system. in the block access mode, the ie signal is ignored. wait: this output pin enables interface to the mpu in the block access mode. to cause the msm5424331 to operate in the block access mode, set the d/f pin high and afterward set ras low. the output of the wait pin goes low while a row or column address is set. perform the actual read or write operation in the block access mode after the output of the wait pin goes high again.
feds5424331-01 1 semiconductor msm5424331 10/34 operation mode fifo mode the fifo mode is set when the d/f pin is set low. 1. write 1.1 write operation before the write operation begins, x address (or line address) must be input to set the initial bit address for the following serial write access. when lwe or uwe is low, a set of serial write data on din0-11 or din12- 23 is written into write registers attached to the dram memory arrays temporarily on the rising edge of wclk. the lwe pin controls the write operation of din0 to din11 (12 bits) and the uwe pin controls the write operation of din12 to din23 (12 bits). following 24-bit-width serial input data is written into the memory locations in the write register designated by an internal write address pointer which is advanced by wclk. this enables continuous serial write on a line. when write clock wclk and read clock rclk are tied together and are controlled by a common clock or clk, more than two msm5424331 can be cascaded directly without any delay devices between the msm5424331 because the read timing is delayed by one clk cycle to the write timing. when the write operation on a line is terminated, be sure to perform a write transfer operation by wr/tr in order to store the written data in the write registers to the corresponding memory cells in the dram memory arrays. 1.2 write address pointer increment operation the write address pointer is incremented synchronously with wclk when lwe or uwe is low. relationship between the lwe , uwe , and ie input levels, write address pointer, and data input status wclk rise lwe uwe ie internal write address pointer data input l l h increments both l- and u-banks. l h h increments the l-bank only. h l h increments the u-bank only. inputted l l l increments both l- and u-banks. l h l increments the l-bank only. h l l increments the u-bank only. h h ? stopped not inputted when lwe or uwe is low and ie is high, the write operation is enabled. if ie level goes low while wclk is active, the write operation is halted but the write address pointer will continue to advance. that is, ie enables a write mask function. when lwe or uwe goes high, the write address pointer stops without wclk.
feds5424331-01 1 semiconductor msm5424331 11/34 2. read 2.1 read operation before the read operation begins, the x address (or line address) must be input for setting initial bit address for the following serial read access. when re is low, a set of serial 24-bit-width read data on do0-11, do12-23 pins is read from read registers attached to dram memory arrays on the rising edge of rclk. each access time is specified by the rising edges of rclk. 2.2 read address pointer increment operation the read address pointer is incremented synchronized with rclk when re level is low. the output data will be undefined when the read address pointer is incremented above the last address of one line. 3. initial address setting (write/read independent) any read operations are prohibited in the read initial address set period. similarly, any write operations are prohibited in the write initial address set period. note that read initial address set and write initial address set can occur independently. similarly, read access can be achieved independently from write initial address set period and write access can be achieved independently from read initial address set cycles. 3.1 write address setting wade/rx enables initial read address inputs. when wade/rx is high, 10 bits of serial x address (or line address) are input from higher order bits from wxad. the operations above enable selection of specific lines randomly and enables the start of serial write access synchronized with write clock wclk. address for each line must be input between each line access. in other words, msm5424331?s write is achieved in a ?line by line? manner. any write operations are prohibited in the initial write address set periods. serial write input enable time t swe must be kept for starting a serial write just after the initial write address set period. the most significant bit (a9) is ignored. 3.2 read address setting rade/rx enables initial read address inputs. when rade/rx is high, 10 bits of serial x address (or line address) are input from higher order bits from rxad. the operations above enable selection of specific lines randomly and enables the start of serial read access synchronized with read clocks, rclk. address for each line must be input between each line access. in other words, msm5424331?s read operation is achieved in ?line by line? manner. any read operations are prohibited in the initial read address set periods. serial read operations are prohibited while rade/rx is high. serial read port enable time t sre must be kept for starting a serial read just after the initial read address set period. the most significant bit (a9) is ignored.
feds5424331-01 1 semiconductor msm5424331 12/34 4. initial address reset modes (write/read independent) the initial address reset modes replace complicated read or write initial address settings with simple reset cycles. initial address reset modes are selected by rr high during read and wr/tr high during write. as in normal read or write address settings, any read operations are prohibited in the read address reset cycles. similarly, any write operations are prohibited in the initial write address reset cycles. note that read initial address reset and write initial address reset can occur independently. similarly, read access can be achieved independently from write initial address reset cycles and write access can be achieved independently from read initial address reset cycles. input addresses are stored into address registers which are connected with address counter which controls address pointer operation. in the serial access operation, the input address into the address registers are kept. serial write data input enable time t swe and serial read port read enable time t sre must be kept for starting serial read or write just after the initial read or write address reset cycles. refer to the ?function table? shown later. 4.1 line hold operation (read only) by the ?line hold operation? logic which is composed by a combination of control inputs? level, access is executed starting from the first word on the current line. 4.2 original address reset operation by the ?original address reset? logic, the address counter is set to (0,0). after the reset mode, serial access starts from the address (0,0) . the address counter is reset by this reset mode but the address register, which stored input address in the previous address reset cycle or address set cycle, is not reset. the non-initialized address can be used as a preset address in ?address jump reset? mode. 4.3 line increment operation by the ?line increment operation? logic, the x address counter is incremented by one from the current x address. that is, serial access from the y = (0) on the next line is enabled. 4.4 address jump operation by the ?address jump operation? logic, a jump may be caused to the initialized line address. note: during one reset setting cycle, a plurality of resets cannot be set.
feds5424331-01 1 semiconductor msm5424331 13/34 block access mode the block access mode is configured when the d/f pin is set high. 1. write operation the msm5424331 fetches a 10-bit row address form lines a0 to a9 at the falling edge of the din0 ( ras ) pin and a 10-bit column address (10 bits long) from the lines at the falling edge of the din1 ( cas ) pin. with this operation, a head address can be set arbitrarily. for a write operation, the lwe or uwe pin must be set low at the falling edge of din0 ( ras ). the actual fetching of write data is performed at the falling edge of din1 ( cas ) after t casb . the write data is entered from i/o pins dq0 to dq11. the write data is written in the l-bank at the falling edge of din0 ( ras ) when lwe is low and uwe is high or in the u-bank when lwe is high and uwe is low. when both lwe and uwe are both low, data is written in either the l- or u-bank (which is undefined). data storage in the memory cell is executed at the rising edge of din0 ( ras ) after the block write operation is completed. when changing a write operation in the fifo mode to a write operation in the block access mode, it is required to monitor on the wait pin whether self refresh in the fifo mode is completed. perform the block write operation after the output of the wait pin is high. the block read operation and fifo operation are disabled during a block write operation. 2. read operation the msm5424331 fetches a 10-bit row address from lines a0 to a9 at the falling edge of the din0 ( ras ) pin and a 10-bit column address from the lines at the falling edge of the din1 ( cas ) pin. with this operation, a head address can be set randomly. for a read operation, the lwe or uwe pin must be set high at the falling edge of din0 ( ras ). read data is fetches at the falling edge of din1 ( cas ) after t casb . the re pin should be set low at the falling edge of din1 ( cas ). the read data is output from dq0 to dq11 i/o pins. the l- or u-bank from which data is read is selected by the status of the ?a9? bit of the row address. data is read from the l-bank when the ?a9? bit is ?0? or from the u-bank when the ?a9? bit is ?1?. when changing a read operation in the fifo mode to a read operation in the block access mode, it is required to monitor on the wait pin whether self refresh in the fifo mode is completed. perform the block read operation after the output of the wait pin is high. the block write operation and fifo operation are disabled during a block read operation. refresh 1. fifo mode in the fifo mode, the msm5424331 performs self refresh. 2. block access mode in the block access mode, self refresh is disabled. use the cas before ras refresh function to refresh. addressing from a0 to a9 pins is not required because refresh addresses are automatically given by the built-in refresh counter.
feds5424331-01 1 semiconductor msm5424331 14/34 power on power must be applied to rclk, wclk, and ie input signals to pull them ?low?, and to re , lwe , uwe , din0 ( ras ), and din1 ( cas ) input signals to pull them ?high? before or when the v cc supply is turned on. after power-up, the device is designed to begin proper operation in at least 200 s after v cc has reached the specified voltage (2.8 v). after 200 s, a minimum of one line dummy write operation and read operation is required according to the address setting mode, because the read and write address pointers are not valid after power-up. after that, an operation can be started in the fifo or block access mode. new data read access in the fifo mode in order to read out ?new data?, the delay between the beginning of a write address setting cycle and read address setting cycle must be at least two lines. old data read access in the fifo mode in order to read out ?old data?, the delay between the beginning of a write address setting cycle and read address setting cycle must be more than 0 but less than a half line.
feds5424331-01 1 semiconductor msm5424331 15/34 function table 1. write (d/f = ?l?) mode no. description of operation wr/tr wxinc wade/rx internal address pointer write transfer 1 write transfer h l l 2 reset h l h x address cleared to (0, 0) 3 line increment h h l x address increment to (xn + 1, 0) address reset mode 4 address jump h h h x address jump to (xi, 0) address setting mode 5 first address setting l l h x address set note: for write, line hold is not provided. 2. read (d/f = ?l?) mode no description of operation rr rxinc rade/rx internal address pointer 1 line hold h l l x address hold to (xn, 0) 2 reset h l h x address cleared to (0, 0) 3 line increment h h l x address increment to (xn + 1, 0) address reset mode 4 address jump h h h x address jump to (xi, 0) address setting mode 5 first address setting l l h x address set
feds5424331-01 1 semiconductor msm5424331 16/34 electrical characteristics absolute maximum ratings parameter symbol condition rating pin voltage v t ta = 25c, with respect to v ss ?0.5 to 4.2 v short circuit output current l os ta = 25c 50 ma power dissipation p d ta = 25c 1 w operating temperature t opr ? 0 to 70c storage temperature t stg ? ?55 to 150c recommended operating conditions (ta = 0 to 70c) parameter symbol min. typ. max. unit power supply voltage v cc 2.8 3.0 3.3 v power supply voltage v ss 000v ?h? input voltage v ih 2.1 v cc v cc + 0.3 v ?l? input voltage v il ?0.5 0 0.8 v dc characteristics (v cc = 2.8 to 3.3 v, ta = 0 to 70c) parameter symbol condition min. max. unit ?h? output voltage v oh l oh = ?0.1 ma 2.2 ? v ?l? output voltage v ol l ol = 0.1 ma ? 0.6 v input leakage current i li 0 < v i < v cc other input voltage 0 v ?10 10 a output leakage current i lo 0 < v o < v cc ?10 10 a power supply current (during operation) i cc1 60 ns cycle ? 90 ma power supply current (during standby) i cc2 input pin = v il /v ih ?5ma capacitance (ta = 25c, f = 1 mhz) parameter symbol max. unit input capacitance c i 7pf output capacitance c o 7pf
feds5424331-01 1 semiconductor msm5424331 17/34 ac characteristics (1/3) fifo mode measurement conditions: (v cc = 2.8 to 3.3 v, ta = 0 to 70c) parameter symbol min. max. unit wclk cycle time t wclk 60 ? ns wclk ?h? pulse width t wwclh 28 ? ns wclk ?l? pulse width t wwcll 28 ? ns serial write address input active set-up time t was 5?ns serial write address input active hold time t wah 7?ns serial write address input inactive hold time t wadh 7?ns serial write address input inactive set-up time t wads 7ns write transfer instruction set-up time t wtrs 5?ns write transfer instruction hold time t wtrh 7?ns write transfer instruction inactive hold time t wtdh 7?ns write transfer instruction inactive set-up time t wtds 7?ns serial write x address set-up time t wxas 5?ns serial write x address hold time t wxah 7?ns serial write data input enable time t swe 1500 ? ns write instruction set-up time t wes 5?ns write instruction hold time t weh 7?ns write instruction inactive hold time t wedh 7?ns write instruction inactive set-up time t weds 7?ns input data set-up time t ds 5?ns input data hold time t dh 12 ? ns wr/tr-wclk active set-up time t wrs 5?ns wr/tr-wclk active hold time t wrh 7?ns wr/tr-wclk inactive hold time t wrdh 7?ns wr/tr-wclk inactive set-up time t wrds 7?ns wxinc-wclk active set-up time t wins 5?ns wxinc-wclk active hold time t wlnh 7?ns wxinc-wclk inactive hold time t windh 7?ns wxinc-wclk inactive set-up time t winds 7?ns wade/rx-wclk active set-up time t wrxs 5?ns wade/rx-wclk active hold time t wrxh 7?ns wade/rx-wclk inactive hold time t wrxdh 7?ns wade/rx-wclk inactive set-up time t wrxds 7?ns ie enable set-up time t ies 5?ns ie enable hold time t ieh 7?ns ie disable set-up time t ieds 7?ns ie disable hold time t iedh 7?ns
feds5424331-01 1 semiconductor msm5424331 18/34 ac characteristics (2/3) fifo mode measurement conditions: (v cc = 2.8 to 3.3 v, ta = 0 to 70c) parameter symbol min. max. unit rclk cycle time t rclk 60 ? ns rclk ?h? pulse width t wrclh 28 ? ns rclk ?l? pulse width t wrcll 28 ? ns serial read address input active set-up time t ras 5?ns serial read address input active hold time t rah 7?ns serial read address input inactive hold time t radh 7?ns serial read address input inactive set-up time t rads 7?ns serial read x address set-up time t rxas 5?ns serial read x address hold time t rxah 7?ns re enable set-up time t res 5?ns re enable hold time t reh t ac ?ns re disable hold time t redh 7?ns re disable set-up time t reds 7?ns read port read enable time t sre 1500 ? ns read port read data hold time t oh 12 ? ns access time from rclk t ac ?50ns read data hold time from re t ddre 12 ? ns rr-rclk active set-up time t rrs 5?ns rr-rclk active hold time t rrh 7?ns rr-rclk inactive hold time t rrdh 7?ns rr-rclk inactive set-up time t rrds 7?ns rxinc-rclk active set-up time t rins 5?ns rxinc-rclk active hold time t rinh 7?ns rxinc-rclk inactive hold time t rindh 7?ns rxinc-rclk inactive set-up time t rinds 7?ns rade/rx-rclk active set-up time t rrxs 5?ns rade/rx-rclk active hold time t rrxh 7?ns rade/rx-rclk inactive set-up time t rrxds 7?ns rade/rx-rclk inactive hold time t rrxdh 7?ns block-fram mode change set-up time t dfs 20 ? ns block-fram mode change hold time t dfh 5?ns transition time (rise and fall) t t 230ns
feds5424331-01 1 semiconductor msm5424331 19/34 ac characteristics (3/3) block mode measurement conditions: (v cc = 2.8 to 3.3 v, ta = 0 to 70c) parameter symbol min. max. unit d/f to ras precharge time t drp 60 ? ns d/f to cas precharge time t dcp 60 ? ns block mode set-up time t bs 40000 ? ns row address set-up time t asr 0?ns row address hold time t ahr 10 ? ns column address set-up time t asc 0?ns column address hold time t ahc 15 ? ns ras to cas delay time t rcd 20 35 ns cas to ras precharge time t crp 10 ? ns cas pulse width t cas 28 ? ns cas precharge time t cp 28 ? ns block mode start to cas pulse width t casb 600 ? ns block mode cycle time t bc 60 ? ns ras precharge time (write) t rpw 400 ? ns ras precharge time (read) t rpr 60 ? ns access time from ras t rac ? 600 ns access time from cas t bac ?50ns data-in set-up time t bds 0?ns data-in hold time t bdh 15 ? ns data-in hold time (head bit) t fbdh 585 ? ns block mode write hold time t bwh 15 ? ns block mode read hold time t brh 15 ? ns write command set-up time t wcs 0?ns write command hold time t wch 15 ? ns read command set-up time t rcs 0?ns read command hold time t rch 15 ? ns ras hold time t rsh 50 ? ns output data hold time from re t ddre 12 ? ns output data enable time from re t dere ?40ns output buffer turn-off delay time t off 12 ? ns read data hold time from cas t boh 15 ? ns write command set-up time from cas t cwcs 0?ns write command hold time from cas t cwch 15 ? ns ras precharge to cas active time ( cas before ras )t rpc 10 ? ns ras pulse width ( cas before ras )t rasb 400 ? ns cas before ras cycle time ( cas before ras )t rc 465 ? ns ras precharge time ( cas before ras )t rp 61 ? ns cas set-up time ( cas before ras )t csr 10 ? ns cas hold time ( cas before ras) t chr 15 ? ns cas precharge time ( cas before ras )t cpn 28 ? ns transition time (rise and fall) t t 230ns
feds5424331-01 1 semiconductor msm5424331 20/34 note: measurement conditions input pulse level : v ih = 2.1 v, v il = 0.8 v input timing reference level : v ih = 2.1 v, v il = 0.8 v output timing reference level : v oh = 2.2 v, v ol = 0.6 v input rise/fall time : 2 ns load condition : cl = 30 pf
feds5424331-01 1 semiconductor msm5424331 21/34 timing waveform (fifo mode) write cycle (address setting cycle) w clk t wclk t wwcll t wwclh t wadh t was t wah t wads valid a 8 valid a 1 valid a 0 valid a 9 valid valid low low t wxas t wxah t wedh t wes t iedh t ies w ade/rx w xad l we u we ie w r/tr w xinc din0 - 11 din12 - 23 t ds t dh t ds t dh t swe ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? t wxah t wxas t wxah t wxas t wxah t wxas t dfs d/f ? ? t dfh
feds5424331-01 1 semiconductor msm5424331 22/34 (fifo mode) write cycle ( lwe / uwe control) wclk t wclk n cycle (n-1)cycle (n-2)cycle (n+2) cycle (n+1) cycle low wade/rx ? ? ie t weh t wedh t weds t wes ? ? ? ? wxinc ? ? lwe uwe ? ? din0 - 11 din12 - 23 ? ? high low wr/tr ? ? low valid d(n+2) valid d(n+1) valid d(n) valid d(n-1) valid d(n-2) valid d(n-3) d/f ? ? low write cycle (ie control) wclk low wade/rx ? ? lwe uwe t ieh t ieds t iedh t ies ? ? ? ? wxinc ? ? ie ? ? din0 - 11 din12 - 23 ? ? low low wr/tr ? ? low valid d(n+3) valid d(n+2) valid d(n) valid d(n-1) valid d(n-2) valid d(n-3) t wclk n cycle (n-1)cycle (n-2)cycle (n+3) cycle (n+2) cycle d/f ? ? low note: in the ie = ?l? cycle, the write address pointer is incremented, though no din data is written and the memory data is held.
feds5424331-01 1 semiconductor msm5424331 23/34 (fifo mode) write cycle (write transfer) w clk t wclk n cycle (n-1)cycle (n-2)cycle t wtdh t wtrs t wtrh t wtds low w ade/rx ? ? w r/tr t weh t weds ? ? ? ? w xinc ? ? lwe uwe ? ? din0 - 11 din12 - 23 ? ? low valid d(n) valid d(n-1) valid d(n-2) valid d(n-3) d/f ? ? low note: when finishing the write operation on a line, be sure to perform a write transfer operation because the write data on the line is stored in the memory cell.
feds5424331-01 1 semiconductor msm5424331 24/34 (fifo mode) read cycle (address setting cycle) rclk t rclk t wrcll t wrclh t radh t ras t rah t rads valid b8 valid b1 valid b0 valid b9 valid low low high-z t rxas t rxah t redh t res rade/rx rxad r e rr rxinc do0 - 23 t ac t oh t sre ? ? ? ? ? ? ? ? ? ? ? ? ? ? t rxah t rxas t rxah t rxas t rxah t rxas t dfs d/f ? ? valid t dfh
feds5424331-01 1 semiconductor msm5424331 25/34 (fifo mode) read cycle ( re control) rclk t rclk n cycle (n-1)cycle (n-2)cycle (n+2) cycle (n+1) cycle low rade/rx ? ? rr t reh t reds t redh t res valid d(n+1) t ac high-z ? ? ? ? rxinc ? ? re ? ? do0 - 23 ? ? d/f ? ? low low valid d(n+2) valid d(n-1) valid d(n-3) valid d(n-2) t oh ? low valid d(n) t ddre note: in the cycle of re = ?h?, the read address pointer is not incremented and the output enters the high impedance state.
feds5424331-01 1 semiconductor msm5424331 26/34 (fifo mode) write reset mode w clk t wclk t dfs t wwcll t wwclh ? ? w xinc ? ? din0 - 11 din12 - 23 ? ? valid valid t ds t dh t ds t dh low lwe uwe ? ? w ade/rx t wrxs t wrxh t wrdh t wrs t wrh t wrds ? ? w r/tr ? ? t wrxdh t wrxds t swe t wedh t wes ? d/f ? ? t dfh note: both the line address and word address are set to 0. write line increment mode w clk t wclk t wwcll t wwclh ? ? w ade/rx ? ? din0 - 11 din12 - 23 ? ? valid valid t ds t dh lwe uwe ? ? w r/tr t wrs t wrh t wins t winh ? ? w xinc ? ? t wrdh t wrds t swe t wedh t wes t windh t winds t ds t dh d/f ? ? t dfh t dfs note: the line address is incremented by 1 and the word address is set to 0.
feds5424331-01 1 semiconductor msm5424331 27/34 (fifo mode) write address jump mode wclk t wclk t wwcll t wwclh ? ? din0 - 11 din12 - 23 ? ? valid valid t ds t dh lwe uwe ? ? wade/rx t wrxs t wrxh t wins t winh ? ? wxinc ? ? t wrxdh t wrxds wr/tr t wrs t wrh ? ? t wrdh t wrds t windh t winds t swe t wedh t wes t ds t dh t dfs d/f ? ? t dfh note: the line address is reset to the initialized addresses and the word address is set to 0.
feds5424331-01 1 semiconductor msm5424331 28/34 (fifo mode) read line hold mode rclk t rclk t wrcll t wrclh ? ? rxinc ? ? do0 - 23 ? ? valid valid t ac t oh low re ? ? t rrdh t rrs t rrh t rrds rr ? ? t sre t redh t res rade/rx ? ? low t dfs d/f ? ? t dfh high-z note: the line address is held and the word address is set to 0. read reset mode rclk t rclk t wrcll t wrclh ? ? rxinc ? ? do0 - 23 ? ? valid valid t ac t oh low re ? ? rade/rx t rrxs t rrxh t rrdh t rrs t rrh t rrds ? ? rr ? ? t rrxdh t rrxds t sre t redh t res t dfs d/f ? ? t dfh high-z note: both the line address and word address are set to 0.
feds5424331-01 1 semiconductor msm5424331 29/34 (fifo mode) read line increment mode rclk t rclk t wrcll t wrclh ? ? rxinc ? ? do0 - 23 ? ? valid valid t ac t oh low re ? ? rade/rx t rrs t rrh t rindh t rins t rinh t rinds ? ? rr ? ? t rrdh t rrds t sre t redh t res t dfs d/f ? ? t dfh high-z note: the line address is incremented by 1 and the word address is set to 0. read address jump mode rclk t rclk t wrcll t wrclh ? ? rxinc ? ? do0 - 23 ? ? valid valid t ac t oh re ? ? rade/rx t rrs t rrh t rindh t rins t rinh t rinds ? ? rr ? ? t rrdh t sre t redh t res t rrds t rrxs t rrxh t rrxdh t rrxds t dfs d/f ? ? t dfh high-z note: the line address is reset to the initialized addresses and the word address is set to 0.
feds5424331-01 1 semiconductor msm5424331 30/34 (block access mode) write cycle data-in n+1 data-in n+2 data-in n+3 data-in n+4 data-in n+5 data-in n+6 data-in n+7 data-in n column t bs t drp t bwh t dcp t crp t rcd t casb t bc t cp t cas t rsh t rpw t ahr t asr row t asc t ahc t wch t wcs t cwcs t bds t fbdh t bds t bdh t bds t bdh t bdh t bdh t bdh t bdh t bdh t bds t bds t bds t bds t bds open open t cwch t wcs d/f w ait r as c as a ddress l we u we dq0 - 11 row note: data is written to l-bank if lwe = ?l? during a falling edge of ras or is written to u-bank if uwe = ?l?. a data write to l-bank or to u-bank is undefined if lwe and uwe = ?l?.
feds5424331-01 1 semiconductor msm5424331 31/34 (block access mode) read cycle data-out n column t bs t drp t brh t dcp t crp t rcd t casb t bc t cp t cas t rsh t rpr t ahr t asr row t asc t ahc t rch t rcs t dere t boh open open t rcs d/f w ait r as c as a ddress l we u we dq0 - 11 row data-out n+1 data-out n+2 data-out n+3 data-out n+4 data-out n+5 data-out n+6 data-out n+7 t boh t boh t boh t boh t boh t boh t bac t bac t bac t bac t bac t bac t bac r e t rac t off t ddre note: read data is read from l-bank if a9 of the row address is ?0? and is read from u-bank if a9 of the row address is ?1?.
feds5424331-01 1 semiconductor msm5424331 32/34 (block access mode) cas before ras refresh cycle open t off t rpc t cpn t csr t chr t rasb t rc t rp t rp high d/f w ait ras cas re dq0 - 11 high
feds5424331-01 1 semiconductor msm5424331 33/34 package dimensions (unit: mm) tsop(2)70-p-400-0.50-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 0.49 typ. 5 rev. no./last revised 2/nov. 13, 1998 notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
feds5424331-01 1 semiconductor msm5424331 34/34 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2000 oki electric industry co., ltd.

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